1. Field of the Invention
The present invention relates to a phase difference detector, which can detect even a very small phase difference between two signals being compared while having no effects upon sources of the signals.
2. Description of Prior Arts
U.S. Pat. No. 3,328,688 issued to Brooks on June 27, 1967 shows the phase difference detector, in which there is provided a pair of flip-flops. One of the two input signals is led to a set terminal of one of the flip-flops through an inverter and directly to a set terminal of the other flip-flops. The other input signal is applied to a clear terminal of the one flip-flop directly and to a clear terminal of the other flip-flop through another inverter. Both set outputs of these flip-flops are given to an AND gate and both reset outputs thereof to another AND gate. In such, arrangement, the trailing edge of the one input signal is compared in the one flip-flop with the leading edge of the other input signal, and the leading edge of the one input signal is compared in the other flip-flop with the trailing edge of the other input signal. When the one input signal leads the other input signal, an output signal appears at an output terminal of the AND gate, while in the opposite case the output is produced at an output terminal of the other AND gate. The patent to Brooks can provide such a phase detector as has a zero output for a matched phase condition. This phase detector, however, has various disadvantages as discussed below.
If the phase difference between the two input signals to be compared becomes extremely small, e.g. less than one nanosecond, the phase detector as mentioned above can no longer detect the difference, that is to say, it has a nonsensitive zone for such a small phase difference. This results from the delay time which always occurs in each of the logic elements when the signal passes therethrough. The delay of this kind is unavoidable, even if logic elements with high responsibility are used. According to the inventers' experience, when a so-called Transistor Transistor Logic (TTL) element was used, the detectable phase difference was to the extent of six nanoseconds. This capability can not be heightened more than one nanosecond even by making use of an Emitter Coupled Logic (ECL) element which is generally regarded as the highest speed one among the logic elements used practically at present.
Further, there is a second disadvantage in that, as is clear from the above description of the arrangement, every input signal must drive two loads. In other words, the two flip-flops are connected in parallel to the one signal source. In this circuit arrangement, therefore, the leading edge and the trailing one of the input signal are delayed or distorted, since the load is quite heavy, and such delay or distortion in the waveform of the input signal depends on the load. This delay or distortion results in a serious error of the phase difference detection. Accordingly, for the purpose of the detection of an extremely small phase difference, it is most desirable that the load against the signal source be as light as possible.
Japanese laid-open patent application 50-156969 published on Dec. 18, 1975 provides a phase detector of another type. In this phase detector, one of the two input signals is compared in a first comparator with a signal which is delayed by a predetermined time with respect to the other input signal, and a second comparator compares the other input signal with a signal which is delayed by a predetermined time with respect to the one input signal. According to this detector, when the one input signal leads the other input signal, the first comparator produces an output pulse, and when the other input signal leads the one input signal, the second comparator produces the output pulse. The width of the output pulse, in both cases, is equal to the sum of the phase difference between the two input signals and the predetermined delay time. If, therefore, the phase difference is zero, the first and second comparators produce simultaneously the output pulses and width of which is equal to each other and to the predetermined delay time. Accordingly, the phase difference can be detected without any nonsensitive zone, no matter how small the difference may be.
This phase detector, however, has the same disadvantage as described as the second disadvantage in the patent to Brooks, because the two load are connected in parallel to one signal source.
In addition to the Japanese laid-open patent application mentioned above, the phase difference detector or phase comparators which have the delay elements are disclosed in following two U.S. patents, so far as the inventors know:
U.S. Pat. No. 3,521,172 issued to G. L. Harmon on July 21, 1970 "Binary Phase Comparator" PA1 U.S. Pat. No. 3,600,690 issued to C. G. White on Aug. 17, 1971 "Phase Difference Detectors"
In essence, the circuit arrangements of both U.S. patents described above are similar to that of the Japanese laid-open patent application 50-15696. Accordingly, these also have the disadvantage that the load against the signal source is heavy.